1. Field of the Invention
The present invention relates to the fabrication of integrated circuit structures, and more particularly to the fabrication of low defect DMOSFETs and associated termination structures.
2. Description of Related Art
Power MOSFET devices enjoy widespread use in such applications as automobile electrical systems, power supplies, and power management applications. Many such devices are commercially available, but an illustrative device is product number SMP60N05, available from Siliconix incorporated, Santa Clara, Calif. This device is an N-channel enhancement mode transistor packaged in a TO-220AB case. The technology used to fabricate the SMP60N05 product is characterized by a specific on-resistance of 3.5 milliohms-cm.sup.2.
Many different processes have been used for the fabrication of power MOSFET devices over the years. These are generally deep diffusion processes. For example, in one early process disclosed in Great Britain Patent Application Publication No. 2 033 658 A, published May 21, 1980 and naming Lidow et al. as coinventors, a p+ tub region is about 4 microns deep and a p+ body region is about 3 microns deep. The cell configuration is hexagonal.
The technology used to fabricate the SMP60N05 product typically achieves junction depths rangeing from 2.5 to 5 microns for the body, from 5 to 6 microns for the p+ body contact, and from 0.5 to 1 micron for the n+ source regions. The cell configuration is square.